An embedded device including a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) device has various kinds of transistors as its main constituent elements. Such constituent transistors need gate dielectric layers having different thicknesses. To this end, gate dielectric layers having suitable thicknesses are formed by performing an oxidation process two or three times, and repeatedly performing a deglaze process for selectively removing a part of an oxide layer.
However, the repeatedly performed deglaze process may cause a severe loss in the edge of STI (shallow trench isolation) film of some devices, such as a low voltage logic transistor device. This is the so-called hump phenomenon. Such a hump phenomenon causes current leakage in a device, resulting in malfunctioning of the device.
For example, an ONO (Oxide/Nitride/Oxide) is deposited to form an ONO layer, and a photoresist for a SONOS transistor is coated. Upper oxide and nitride layers of an ONO layer are removed in the deglaze process, and an oxide layer for a high voltage transistor to program the SONOS device is formed by performing the oxidation process again. Then, regions other than an ultraviolet (UV) region are deglazed. At this time, a loss of STI film occurs in the high voltage region and the low voltage logic region.
Then, an oxide layer for the high voltage logic transistor is formed by performing the oxidation process, and regions other than the high voltage region are deglazed. At this time, the loss of STI film in the low voltage logic region occurs again. Next, an oxidation process is performed to form an oxidation layer for the low voltage logic transistor.
Accordingly, since the deglaze process is performed once in the high voltage device region and at lease two times in the low voltage region, there is accompanied a loss of gap filled oxide, such as an NSG oxide, for the STI film.
FIGS. 1 and 2 are sectional views schematically illustrating a loss of device film caused by a conventional deglaze process.
Referring to FIG. 1, a STI film 15 and a gate dielectric layer 20 are sequentially formed on a semiconductor substrate 10. Subsequently, as shown in FIG. 2, by performing a process to control the thickness of gate dielectric layer 20, for example, by performing a deglaze process repeatedly, an edge 30 of shallow trench isolation 15 is lost, thereby causing a hump phenomenon.
Since such a hump phenomenon causes current leakage of a device, thereby malfunctioning the device, it is thus required to prevent the loss of edge 30 of shallow trench isolation 15. That is, it is strongly needed to develop a method for forming gate dielectric layers having different thicknesses without causing the hump phenomenon.